DRAMs are subjected to qualification testing by some users. One function of the testing is to assess the reliability of the supplier's DRAMs. These tests include techniques which accelerate the occurrence of a failure arising from some defect. One of these tests is the bit stress test. The bit stress test is accomplished by writing a data pattern into the DRAM that results in the same charge polarity being stored in each cell while increasing the supply voltage significantly beyond the normal operating voltage but not so great as to be destructive of a good device. The writing of all of the cells to the same voltage polarity is not quite as straightforward as it might sound. In typical DRAMs, a particular cell is coupled to one bit line but when that cell is accessed, the bit line to which it is coupled is compared to another bit line which is considered its pair. In a folded bit line architecture, the two bit lines which form a pair are adjoining. Each pair of bit lines is comprised of a true bit line and a complementary bit line. The true bit line is considered to be a logic high when it is at the comparatively high voltage and at a logic low when it is at the comparatively low voltage. Just the opposite is true for the complementary bit lines. A comparatively high voltage on a complementary bit line is representative of a logic low, and a relatively low voltage is representative of a logic high.
In order to ensure that all of the cells are written to the same voltage polarity, the cells coupled to true bit lines are written to the opposite logic state of the cells coupled to the complementary bit lines. To perform this test requires knowing which addresses select true bit lines and which select complementary bit lines. This information is included in what is commonly known as the "bit map" of the memory array. The supplier then supplies the user with the bit map which is routinely made available by the supplier. Users who desire to perform the bit stress test can then effectively do so.
There is an additional problem which has not been adequately solved with respect to redundancy. In an array which uses folded bit lines it has been found to be advantageous, for layout density, to have the true complement sequence alternate. The first bit line pair, for example, is arranged true then complement. The next bit line pair is arranged complement then true. This results in each bit line having an adjoining bit line of the same type. Each bit line adjoins two bit lines. One of the adjoining bit lines is its pair and is of the opposite type. The other adjoining bit line is from another pair and is of the same type. Using "C" to designate complementary and "T" to designate true, the sequence of adjoining bit lines is CTTCCTTCCTTC . . . until the normal array is complete. After the normal array is complete, there are redundant columns comprised of bit line pairs. It is desirable, for optimum efficiency of the redundancy, to be able to substitute any redundant column for any defective column. This creates a problem for being able to both ensure a proper bit stress test and retain optimum use of the column redundancy.
This problem is described with reference to FIG. 1 which is a portion of a DRAM array 10 showing two adjacent bit line pairs 11 and 12 and a redundant bit line pair 13. Bit line pair 11 has a true bit line 14, and a complementary bit line 15. Bit line pair 12 has a complementary bit line 16 adjacent to complementary bit line 15, and a true bit line 17. Bit line pair 13 has a true bit line 18 and a complementary bit line 19. Array 10 includes adjacent word lines 21, 22, 23, and 24 which intersect bit line pairs 11-13 and memory cells 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, and 37 located at intersections thereof. Memory cell 26 has an enable input coupled to word line 22, and an input/output (I/O) coupled to true bit line 14. Memory cell 27 has an enable input coupled to word line 24, and an I/O coupled to true bit line 14. Memory cell 28 has an enable input coupled to word line 21, and an I/O coupled to complementary bit line 15. Memory cell 29 has an enable input couple d to word line 23, and an I/O coupled to complementary bit line 15. Memory cell 30 has an enable input coupled to word line 22, and an I/O coupled to complementary bit line 16. Memory cell 31 has an enable input coupled to word line 24, and an I/O coupled to complementary bit line 16. Memory cell 32 has an enable input coupled word line 21, and an I/O coupled to true bit line 17. Memory cell 33 has an enable input coupled to word line 23, and an I/O coupled to true bit line 17. Memory cell 34 has an enable input coupled to word line 22, and an I/O coupled to true bit line 18. Memory cell 35 has an enable input coupled to word line 24, and an I/O coupled to true bit line 18. Memory cell 36 has an enable input coupled to word line 21, and an I/O coupled to complementary bit line 19. Memory cell 37 has an enable input coupled to work line 24, and an I/O coupled to complementary bit line 19. Array 10 includes a sense amplifier 41 coupled to bit line pair 11, a sense amplifier 42 coupled to bit line pair 12, and a sense amplifier 43 coupled to bit line pair 13. Array 10 has coupling transistors 45, 46, 47, 48, 49, and 50 for coupling bit line pairs 11-13 to a data line pair 51. Data line pair 51 has a true data line 52, and a complementary data line 53. Transistors 45, 48, and 49 selectively couple true data line 52 to true bit lines 14, 17, and 18, respectively. Transistors 46, 47, and 50 selectively couple complementary data line 53 to complementary bit lines 15, 16, and 19, respectively. Any bit line which is selectively coupled to true data line 52 is a true bit line, whereas any bit line which is selectively coupled to complementary data line 53 is a complementary bit line.
To implement redundancy in array 10 using bit line pair 13 to replace either bit line pair 11 or 12 creates a problem with respect to the bit stress test. Replacing bit line pair 11 with bit line pair 13 is not a problem. For example, if word line 22 is enabled, then memory cells 26 and 34, which are both coupled to a true bit line, are enabled. Thus the address which selects replaced true bit line 14 also selects a true bit line in the redundant bit line pair. Similarly, if word line 23 is enabled, memory cells 29 and 37, which are coupled to complementary bit lines, are enabled. Thus, the address which selects replaced complementary bit line 15 selects a complementary bit line in the redundant bit line pair. Thus, bit line pair 13 can replace bit line pair 11 without adversely affecting the bit stress test.
On the other hand, if bit line pair 13 replaces bit lines pair 12, there is a problem. If word line 22 is enabled then memory cells 30 and 34 are enabled. Memory cell 30 is coupled to complementary bit line 16, whereas memory cell 34 is coupled to true bit line 18. Thus for the address which selects cell 30, word line 22 is enabled and would normally result in the I/O of the cell being coupled to complementary data line 53, but with bit line pair 13 replacing bit line pair 12, memory cell 34 is selected so that the I/O of memory cell 34 is coupled to true data line 52. This means that the address which normally has a comparatively high voltage to represent a logic low now has a comparatively low voltage to represent a logic low. This is not a problem for general use, but it is for the bit stress test. Although it is possible to keep records for each device as to the nature of any changes in its bit map resulting from implement any redundant columns, such an approach would be very cumbersome for both the supplier and the user. The approach in the past has been to either constrain the replacement of defective bit line pairs with ones of the same orientation or to simply not provide for a completely effective bit stress test for devices in which redundancy has been implemented.